--- title: "Member of Technical Staff, Sandbox Infrastructure" company: "SF Tensor" company_url: "https://www.remjobs.works/companies/sf-tensor" url: "https://www.remjobs.works/job/sf-tensor-member-of-technical-staff-sandbox-infrastructure-a81f80c9-2f5f-49b3-9f3e-812265965614" apply_url: "https://jobs.ashbyhq.com/sf-tensor/7768fa39-742a-41dc-b329-edf75cdcd168" workplace: onsite location: "San Francisco" employment_type: full-time seniority: staff role: devops-infrastructure region: united-states skills: ["cpp", "linux", "rust"] date_posted: 2026-08-29T20:33:24.538Z first_seen_by_remjobs: 2026-08-31T08:42:25.942Z --- # Member of Technical Staff, Sandbox Infrastructure **SF Tensor** — San Francisco Apply: https://jobs.ashbyhq.com/sf-tensor/7768fa39-742a-41dc-b329-edf75cdcd168 ## About SF Tensor AI researchers should be pushing the boundaries of what's possible with new architectures and training methods. Instead, they waste weeks configuring cloud infrastructure, debugging distributed systems, and optimizing their GPU code. We know because we lived it: While training our own models across thousands of GPUs earlier this year, we spent more time fighting our infrastructure than doing actual research. That's why we're building two things. First, Elastic Cloud: a managed platform that automatically finds the cheapest GPUs across all providers, handles spot instance preemption, and cuts compute costs by up to 80%. Second, automatic kernel optimization that makes training code run faster by modeling hardware topology, often beating hand-tuned implementations. The problem is that getting high performance across different hardware is genuinely hard. NVIDIA's CUDA moat exists because writing fast kernels requires deep expertise. Most teams either accept vendor lock-in or hire expensive kernel engineers. Our goal is to break the CUDA moat. The compute bottleneck is the biggest constraint on AI progress. NVIDIA can't manufacture enough GPUs, and their monopoly keeps prices astronomical. Meanwhile, AMD, Google, and Amazon are shipping capable alternative hardware that nobody uses because the software is too hard. We're breaking that moat. If we succeed, anyone will be able to train state-of-the-art models without thinking past their PyTorch code. ## About the role ### At SF Tensor, we're building the future of high-performance compute We firmly believe that the future of AI depends on the unglamorous: rethinking and rebuilding the stack, all the way down. From the hardware underneath it to the compiler targeting it and the cloud running it. Right now those three things fight each other and that friction shows up as a tax on every researcher trying to build something ambitious. We're here to axe that tax and make compute faster, cheaper and more available. When we succeed, compute will be portable enough that "which cloud, which chip" stop being something you worry about. To achieve this, we are building our Kernel Optimizer, which takes code and finds its fastest possible form for whatever vendor and cluster topology you point it at, automatically, as well as the Model Foundry which manages the runs, makes research easier and moves workloads across clouds and chips as prices and availability ship, instead of leaving you locked into whatever vendor you signed with first. We're backed by Susa Ventures, Y Combinator, along with some great funds and angels including Max Mullen and Paul Graham, as well as founders and executives at Neuralink, Notion and AMD. We're looking for researchers, engineers and organizations who agree with the basic premise: you don't get the next leap in AI without a leap in compute first. #### About the Role We build the fastest GPU compiler in the world. Most compilers have to preserve correctness at every transform, constraining how far they can search, while we prove correctness at the end instead, allowing us to search a far wider space, with agents, with RL, with anything that works and still guarantee the result. It's why we hold #1 on NVIDIA's own kernel benchmark across hundreds of production kernels. For our search to work, we need to run an enormous amount of untrusted, freshly generated kernels on real silicon, quickly and safely, which is why we're hiring a Member of Technical Staff for Sandbox Infrastructure to build the layer that makes it possible: a serverless GPU container service across NVIDIA, AMD, TPU and Trainium, at a scale and fidelity nobody sells off the shelf. It needs to run three things: (1) our compiler measures every candidate program inside it, so a noisy or unfair sandbox directly corrupts the reward signal the search learns from, (2) our own post-training runs inside it (e.g., when we RL a model on AMD kernel engineering, every rollout is in a sandbox) and (3) customer workloads that require isolation, such as their RL rollouts, run on it too. We already do this on NVIDIA and AMD, including having rolled AMD GPU support in gVisor [from scratch](https://x.com/BenKoska/status/2086211029713965099). The work now is depth and breadth, adding support for more vendors, higher fidelity instrumentation, faster cold starts and more features. A lot of our sandboxes need to run on spot pools without losing works, they can span multiple GPUs and sometimes multiple nodes, they need to survive failure and preemption as well as live-migration (which our stack does while keeping sockets intact so that instances can relocate mid-flight while still streaming data in or out without a hiccup). #### What You'll Do - You'll extend our sandboxing stack to new vendors and accelerators - You'll build and maintain GPU virtualization below the runtime, including gVisor work at the driver and ioctl level - You'll make sandboxes first-class citizens on spot capacity, which means preemption-aware scheduling, checkpointing and rescheduling - You'll support multi-GPU and multi-node sandboxes, including the interconnect (NVLink, NVSwitch) and RDMA paths (InfiniBand, RoCE) paths those require - You'll own live migration end-to-end, including our socket-preserving migration - You'll guarantee measurement and profiling fidelity as well as their isolation - You'll work directly with the compiler, post-training and kernel teams to ensure their throughput is not capped by sandboxes #### What We're Looking For - Someone with strong low-level systems engineering background: Linux kernel internals, containers, namespaces, cgroups, syscall interception or hypervisors - Someone with experience in GPU systems engineering: drivers, runtimes or scheduling on accelerator fleets - Someone comfortable with distributed systems failure modes: preemption, partial failure, checkpoint/restore and dealing with states you can't afford to loose - Someone proficient in Go, C/C++ or Rust - Someone with a strong bias toward building the thing yourself when no vendor supports what you need #### Nice to Have - Someone who's worked directly with gVisor, Firecracker, Kata, QEMU/KVM or similar - Someone who's worked directly on CRIU, -live migration or connection-preserving failover work - Someone familiar with NCCL/RCCL, RDMA, InfiniBand or vendor interconnects - Someone who's run large fleets on spot or other preemptible capacity - Someone familiar with bare-metal provisioning, hypervisors or fleet management at scale - Someone with a security background in isolation boundaries and untrusted code execution #### Why Join Us Most "serverless GPU" products stop at running a container on a GPU. Our's runs arbitrary code across four vendors, on spot capacity, across multiple nodes with migration that keeps live sockets open and timings clean enough to use as an RL reward. It's a hard systems problem and it's directly load-bearing, because the faster and more reliable the sandboxes, the more programs our compiler can search and the faster our models train the same week. We're a small team operating at frontier scale. We pre-trained foundation models on 4,000 AMD GPUs as a team of three, designed and brought up GB300 NVL72 clusters and designed a TOP500 supercomputer. We believe that hard problems get solved in person and most of our work happens at our office in San Francisco. We offer relocation assistance and, where possible, we'd like you here as often as possible. The base salary range for this full-time position is $275,000-$315,000, plus meaningful equity and benefits. --- Source: SF Tensor's own career page, read by RemJobs. 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