--- title: "Member of Technical Staff, Post-Training & Applied Research" company: "SF Tensor" company_url: "https://www.remjobs.works/companies/sf-tensor" url: "https://www.remjobs.works/job/sf-tensor-member-of-technical-staff-post-training-applied-research-1ebb9eaf-cd64-46a3-aae4-62c1b80e73b9" apply_url: "https://jobs.ashbyhq.com/sf-tensor/9232c990-4435-45f9-8002-721f52aab5be" workplace: onsite location: "San Francisco" employment_type: full-time seniority: staff role: software-engineering region: united-states skills: ["pytorch"] date_posted: 2026-08-29T20:38:58.274Z first_seen_by_remjobs: 2026-08-31T08:42:25.942Z --- # Member of Technical Staff, Post-Training & Applied Research **SF Tensor** — San Francisco Apply: https://jobs.ashbyhq.com/sf-tensor/9232c990-4435-45f9-8002-721f52aab5be ## About SF Tensor AI researchers should be pushing the boundaries of what's possible with new architectures and training methods. Instead, they waste weeks configuring cloud infrastructure, debugging distributed systems, and optimizing their GPU code. We know because we lived it: While training our own models across thousands of GPUs earlier this year, we spent more time fighting our infrastructure than doing actual research. That's why we're building two things. First, Elastic Cloud: a managed platform that automatically finds the cheapest GPUs across all providers, handles spot instance preemption, and cuts compute costs by up to 80%. Second, automatic kernel optimization that makes training code run faster by modeling hardware topology, often beating hand-tuned implementations. The problem is that getting high performance across different hardware is genuinely hard. NVIDIA's CUDA moat exists because writing fast kernels requires deep expertise. Most teams either accept vendor lock-in or hire expensive kernel engineers. Our goal is to break the CUDA moat. The compute bottleneck is the biggest constraint on AI progress. NVIDIA can't manufacture enough GPUs, and their monopoly keeps prices astronomical. Meanwhile, AMD, Google, and Amazon are shipping capable alternative hardware that nobody uses because the software is too hard. We're breaking that moat. If we succeed, anyone will be able to train state-of-the-art models without thinking past their PyTorch code. ## About the role ### At SF Tensor, we're building the future of high-performance compute We firmly believe that the future of AI depends on the unglamorous: rethinking and rebuilding the stack, all the way down. From the hardware underneath it to the compiler targeting it and the cloud running it. Right now those three things fight each other and that friction shows up as a tax on every researcher trying to build something ambitious. We're here to axe that tax and make compute faster, cheaper and more available. When we succeed, compute will be portable enough that "which cloud, which chip" stop being something you worry about. To achieve this, we are building our Kernel Optimizer, which takes code and finds its fastest possible form for whatever vendor and cluster topology you point it at, automatically, as well as the Model Foundry which manages the runs, makes research easier and moves workloads across clouds and chips as prices and availability ship, instead of leaving you locked into whatever vendor you signed with first. We're backed by Susa Ventures, Y Combinator, along with some great funds and angels including Max Mullen and Paul Graham, as well as founders and executives at Neuralink, Notion and AMD. We're looking for researchers, engineers and organizations who agree with the basic premise: you don't get the next leap in AI without a leap in compute first. #### About the Role We build the fastest GPU compiler in the world. Most compilers have to preserve correctness at every transform, constraining how far they can search, while we prove correctness at the end instead, allowing us to search a far wider space, with agents, with RL, with anything that works and still guarantee the result. It's why we hold #1 on NVIDIA's own kernel benchmark across hundreds of production kernels. Speed at the kernel layer is only worth what we do with it though and our enterprise offering promises we'll turn a customer's dataset into a specialist model in days. To do that we run SFT, RL, DPO, design evals and distillation down to smaller and edge-deployable models. We're hiring a Member of Technical Staff to own the modeling side of that end to end. The infrastructure you'll be working on top of is unusually strong, which is the only reason we're able to train models so fast. Every experiment goes through Model Foundry, which let's you run experiments on the best hardware, look at overviews or dive deep into any detail all in a versioned and reproducible manner, making it trivial to reuse and modify recipes. Underneath that is the most powerful engine you could ask for, which has been used to post-train multi-100B language parameter models on TPU, post-train robotics models on Trainium and pre-train AlphaFold v3 on AMD. #### What You'll Do - You'll own the post-training pipeline end-to-end: data curation, SFT, preference optimization, RL, evals, distillation and finally deployment - You'll design reward functions and RL looks along customer domain experts, who know the task inside-out but not our training stack - You'll build an eval harness trustworthy enough to make a ship/no-ship call within a short window, especially where the target is subjective taste rather than a scored benchmark - You'll structure and generate datasets, including synthetic data pipelines, from whatever the customer actually has - You'll distill specialist models down into smaller models - You'll drive the time-to-model, which means finding what's actually on the critical path and removing it, run after run - You'll embed with customers as a forward-deployed researcher, then hand the pipeline over cleanly when their team is ready to take over #### What We're Looking For - Someone who's shipped post-trained models into production and can talk honestly about the tradeoffs - Someone with hands-on depth across SFT and RL (DPO, GRPO, PPO or similar) - Someone who can judge evaluation honestly: what to measure, what a result means and when a number is lying to you - Someone who's comfortable owning data: curation, filtering, labeling workflows and synthetic generation - Someone proficient in PyTorch or JAX - Someone willing to sit with customers' domain experts to turn their intuition into a reward function #### Nice to Have - Someone who's worked on RL infrastructure at scale: rollout engines, distributed training or throughput debugging - Someone with experience in distillation, quantization and speculative decoding - Someone who's post-trained for agents and tool use - Someone who's been forward-deployed or has customer-facing engineering experience #### Why Join Us Most post-training people spend most of their time fighting infrastructure that they don't control and your ideas are never the bottleneck, the ability to execute them is. We invest heavily into integrating AI tooling into our infrastructure and model foundry to speed up the research process and get you from idea → result as fast as possible. Beyond that, the people who wrote the rollout engine, the inference engine and the kernels under both are the same people you eat lunch with, so if your run is slow, a fix is a conversation and not a ticket. We're a small team operating at frontier scale. We pre-trained foundation models on 4,000 AMD GPUs as a team of three, designed and brought up GB300 NVL72 clusters and designed a TOP500 supercomputer. We believe that hard problems get solved in person and most of our work happens at our office in San Francisco. We offer relocation assistance and, where possible, we'd like you here as often as possible. The base salary range for this full-time position is $275,000-$315,000, plus meaningful equity and benefits. --- Source: SF Tensor's own career page, read by RemJobs. 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