---
title: "Principal Physical Design Engineer"
company: "Celero Communications, Inc."
company_url: "https://www.remjobs.works/companies/celero-communications-inc"
url: "https://www.remjobs.works/job/celero-communications-inc-principal-physical-design-engineer-1d0cfb59-f090-44c2-9508-c092efe84285"
apply_url: "https://job-boards.greenhouse.io/celerocommunicationsinc/jobs/4372151009"
workplace: onsite
location: "San Jose, CA"
employment_type: unspecified
seniority: principal
role: software-engineering
region: united-states
skills: ["python"]
date_posted: 2026-08-17T17:30:57.000Z
first_seen_by_remjobs: 2026-09-15T17:02:17.985Z
---

# Principal Physical Design Engineer

**Celero Communications, Inc.** · San Jose, CA

Apply: https://job-boards.greenhouse.io/celerocommunicationsinc/jobs/4372151009

## About the role

Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure.

We are seeking an experienced **Physical Design Engineer** to lead the transformation of complex circuit designs into high-quality, manufacturable silicon. In this role, you will drive all aspects of the physical implementation flow, including floorplanning, power planning, place-and-route (P&R), clock tree synthesis, timing closure, and physical verification. You will collaborate closely with architecture, RTL, circuit design, and verification teams to deliver high-performance chips that meet aggressive targets for performance, power, area (PPA), signal integrity, and manufacturability. As a technical leader, you will help define physical design methodologies, mentor engineers, and ensure successful tape-out of next-generation semiconductor products.

**Locations**: San Jose, CA (preferred) or Irvine, CA (HQ)

**Core Responsibilities**
• RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs) or complex digital blocks.
• Design Optimization: Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance.
• Design Convergence: Resolve timing, congestions, EM/IR issues together with Frontend Designers
• Signoff & Verification: Run Static Timing Analysis (STA) and physical verification. Fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations.
• Methodology Development: Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl.
• Cross-Functional Leadership: Partner with architects, logic designers, and analog design team for tapeout readiness.

**Key Qualifications**
• Must have 5+ years of relevant ASIC physical design experience (depending on degree level).
• Process Knowledge: Deep tapeout experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm).
• Tool Mastery: Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus, Tempus, Voltus, Pegasus, Calibre).
• Technical Concepts: Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup.

*Annual Base Salary Range: $150,000 to $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)*

---

Source: Celero Communications, Inc.'s own career page, read by RemJobs. Canonical HTML version: https://www.remjobs.works/job/celero-communications-inc-principal-physical-design-engineer-1d0cfb59-f090-44c2-9508-c092efe84285